Emerging Developments in Nanoscale Lithography

Article by Dr. Dirk Weiss, Senior Research Scientist, Washington Technology Center
As the Complementary Metal–Oxide Semiconductor (CMOS) industry transitions in 2007 from 65-nanometer to 45-nanometer structures, emerging developments in extreme ultraviolet (EUV) lithography and nanoimprint lithography (NIL) may advance the industry toward even smaller feature sizes in the next decade. Theses were two of the main topics discussed at the recent SPIE Advanced Lithography Conference in San Jose, California.

While the technology for shifting from 65-nanometer to 45-nanometer structures is available now, the exponential increase in cost-of-ownership for 32-nm technology tools may pose a barrier to further miniaturization.

EUV research for 32-nm technology is aimed at overcoming a variety of challenges of this advanced nanoscale lithography. Ultra-high vacuum systems are required for sub-15-nm-wavelenth radiation. New infrastructures for mask fabrication and metrology must be created. Optical flare, mirror contamination and plasma stability are also issues. New resists are needed to overcome resolution limited by acid diffusion.

Cost is a barrier with 32-nm technology. Compared to the cost of more than $30 million for a modern optical water-immersion scanner for 45-nm technology, the expected price for a EUV scanner for 32-nm technology will approach $100 million.

NIL, which was developed only 10 years ago, represents an even more disruptive approach than EUV. Proponents argue that the lower cost of ownership positions NIL as a viable alternative to EUV for the 32-nm node and beyond. The CMOS industry, however, remains very skeptical. The general consensus is that the first commercial products with nanostructures made by NIL will be non-CMOS applications such as magnetic hard drives, light emitting diodes (LEDs) or sensors.

The NIL process is comparably simple and comes in two types: Ultraviolet (UV)-NIL and thermal NIL. In the former, a transparent (quartz) mold is pressed into a low-viscosity UV-curable resist; the resist is hardened with a flash of UV light before the mold is removed. In the latter, a solid resist is heated above its glass-transition temperature before the molding process. The patterned resist can be either used as an etch mask, or directly incorporated into a device. Thermal NIL is more versatile for patterning a variety of materials, whereas UV NIL has more stringent requirements for the resist such as low viscosity and UV cross-linking properties. UV NIL is performed at room temperature, which eliminates problems associated with differential thermal expansion.

The three main advantages of NIL are the lower cost of ownership, the extremely high resolution (2 nm feature size has been achieved in the laboratory) and parallel fabrication as opposed to the very slow process of serial writing with electron beams or scanning probe microscopy. The main challenges are limited overlay accuracy, relatively high defect density, and mask metrology (mask features are 1:1, whereas features on photomasks are scaled up by a ratio of 4:1). These challenges would be less critical in non-CMOS applications with less-stringent defect tolerance and no or less-stringent overlay requirements.

Products incorporating NIL-patterned nanostructures are not yet found on the market, but there is very high activity in industrial and academic R&D laboratories in developing such applications. The comparably low cost of NIL, which is as low as $500,000 for a basic tool, will position this technology as ideal for small companies and academic applied research environments.

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